Graphene binding on black phosphorus enables high on/off ratios and mobility

ABSTRACT Graphene is one of the most promising candidates for integrated circuits due to its robustness against short-channel effects, inherent high carrier mobility and desired gapless nature for Ohmic contact, but it is difficult to achieve satisfactory on/off ratios even at the expense of its carrier mobility, limiting its device applications. Here, we present a strategy to realize high back-gate switching ratios in a graphene monolayer with well-maintained high mobility by forming a vertical heterostructure with a black phosphorus multi-layer. By local current annealing, strain is introduced within an established area of the graphene, which forms a reflective interface with the rest of the strain-free area and thus generates a robust off-state via local current depletion. Applying a positive back-gate voltage to the heterostructure can keep the black phosphorus insulating, while a negative back-gate voltage changes the black phosphorus to be conductive because of hole accumulation. Then, a parallel channel is activated within the strain-free graphene area by edge-contacted electrodes, thereby largely inheriting the intrinsic carrier mobility of graphene in the on-state. As a result, the device can provide an on/off voltage ratio of >103 as well as a mobility of ∼8000 cm2 V−1 s−1 at room temperature, meeting the low-power criterion suggested by the International Roadmap for Devices and Systems.


INTRODUCTION
Field effect transistors (FETs) are the core elements of current integrated circuits [1 -3 ].Conventional silicon-based FETs are facing critical issues when scaled down to nanometers, such as self-heating [4 ], charge leakages [5 ] and short-channel effects [3 ,6 ].To address these issues, it is of paramount importance to achieve a high on/off ratio that permits effective logical operation at the nanometer size limit and meanwhile hold high carrier mobility that enables low power consumption [7 ].To this end, extensive efforts have been devoted to developing new nanomaterials and designing innovative device architectures [8 ,9 ].
Graphene-a single layer of carbon atoms in a honeycomb lattice-exhibits outstanding carrier mobility ( > 10 4 cm 2 V −1 s −1 ) [10 -12 ], negligible contact resistance [13 ,14 ] and high compatibil-ity with conventional manufacturing processes that mark it as a promising candidate for downscaling logic devices.Yet, the on/off ratio of graphene is commonly < 30 due to its gapless nature and this limits its application in logic devices [3 ,15 -22 ].Several strategies have been reported to increase the on/off ratios by opening a bandgap in the graphene but often at the expense of significantly reduced carrier mobility [23 ].For example, patterning graphene into nanoribbons [24 ] and functionalizing graphene [25 -30 ] can open a sizable bandgap yielding a high on/off ratio of ≤70 but the carrier mobility drops to < 880 cm 2 V −1 s −1 [24 ].In fact, the challenge in achieving a good trade-off between the on/off ratio and carrier mobility has been encountered in silicon and 2D semiconductors as well [31 ].Therefore, it is imperative to find a new approach (especially in engineering device architecture) that can provide high on/off ratios while, to a great extent, maintaining the intrinsic carrier mobility.
Here, we report a new device architecture consisting of a graphene monolayer bound on a black phosphorus (BP) multi-layer, which can offer an on/off ratio of > 10 3 and a mobility close to the intrinsic limit of graphene.In particular, we introduce heterostrain in graphene by local current annealing that results in a reflective interface between the strained and unstrained graphene areas and thus a robust off-state against external magnetic fields and elevated temperature.Then, an applied bias voltage can open a conductive channel in the BP that in turn switches an on-state in the graphene through the electrodes edge-contacting all the atomic layers.Such a device architecture is, in principle, applicable to any highmobility 2D materials bound on a range of semiconducting multilayers and may indicate a new paradigm for fabricating high-performance electronic devices.

GENERATING A REFLECTIVE INTERFACE IN A DUAL-GATED GRAPHENE TRANSISTOR
The device consists of a graphene monolayer stacked on BP (thickness ∼23 nm), which are overall sandwiched between two hexagonal boron nitride (hBN) sheets.The zigzag directions of Gr and BP crystals are well aligned (Fig. 1 a), while the twist angle between the Gr and the hBN was set at ∼15°to diminish unfavorable interlayer interaction.Then, the hBN/Gr/BP/hBN stack was etched to form an Lshaped device (Fig. 1 b) with two channels parallel and perpendicular to the zigzag direction of the BP, respectively.After that, the graphene-based transistor (right panel, Fig. 1 b) was completed by depositing 12 electrodes (indexed as 1-12, see Methods) that edge-contacted all the atomic layers [13 ].The dual gates were realized by using a gold top-gate and a silicon back-gate [32 ,33 ].
A key feature in the as-fabricated transistor is the in-plane reflective interface between the strained and unstrained graphene areas.The strained area between Electrodes 1 and 3 (Fig. 1 b) was created via local current annealing (at 1 mA/ μm) for 120 min at 3 00 K [3 4 -36 ].In our previous work [37 ], graphene on multi-layer BP after thermal annealing was found to undergo non-uniform lattice strain resulting from large lattice mismatch.Figure 1 c shows two representative Raman spectra collected from unannealed and annealed sample regions.The full widths at half maximum (FWHM) of the G peak (at ∼1576.9cm −1 ) and 2D peak (at ∼2677.9cm −1 ) corresponding respectively to highfrequency E 2 g phonon and double-resonance modes broaden for annealed graphene.In accordance with statistical analysis of 38 spectra ( G and 2D , Fig. 1 d), the FWHMs of the G and 2D peaks of the annealed graphene increase to 15 ± 4 and 20 ± 4 cm −1 (red scatters) from 8 ± 2 and 14 ± 4 cm −1 (blue scatters, unannealed region), respectively, evidencing occurrences of local lattice strain after local annealing.Furthermore, the robust D (1340.3 cm −1 ), D' (1615.4cm −1 ) and D + D' (2932.7 cm −1 ) peaks, which are correlated with the breathing modes of the sp 2 rings, are clearly observed in the annealed region [38 -40 ].This enhanced backscattering phenomenon of photo-excited electrons/holes reveals feasible moiré potentials or nano-rippled structures after thermal treatment.In the meantime, charge localization may also be more likely to occur within annealed graphene and produce a reflective interface at the in-plane strain junction (see Supplementary Fig. S3 ) [41 ,42 ].
To unravel the electronic variations induced by local annealing, the differential conductance d ( i and j represent selected electrodes, Fig. 1 b) of a graphene-based transistor as a function of DC-bias ( V bias ) was conducted at 1.5 K.The d I 76 /d V curve (Fig. 1 e) of unannealed graphene shows a 'V' shape with its minimum at V bias = 0 V, consistently with the typical transport behavior of intrinsic graphene [21 ].In contrast, the d I 23 /d V curve (annealed region) reveals a robust peak at | V bias | < 1.5 mV, presumably originating from the charge localization by annealing-induced strain and lattice distortion (see Supplementary Section S2.9 ).To gain more insights, we utilized a parametrizing strain as a pseudo-gauge field to calculate the electronic structure of strained (annealed) and pristine (unannealed) graphene (see Supplementary Section S1.4 ).The band dispersion of unannealed graphene on BP (Fig. 1 f and g) remains linear but becomes nearly flat under strain (Fig. 1 h and i).The theoretical reproduction of differential conductance nicely validates the creation of a reflective interface within the in-plane junction area by local annealing.

UNCONVENTIONAL LONGITUDINAL AND TRANSVERSE TRANSPORT
We next explored the transport behavior of a graphene-based transistor in the Hall-bar configuration, inserted in Fig. 2 a.After injecting current (100 nA) from Electrode 5 to Electrode 1, the longitudinal voltage ( V xx , Electrodes 3 and 2) curve shows an asymmetric transition from approximate zero ( T = 120 K, signal noise level < 0.02 μV limited by lock-in measurement) for a positive back-gate voltage ( V bg ≥ 0 V) to hundreds of microvolts for a negative one ( V bg < 0 V), in contrast to the typical V-shaped curve of intrinsic graphene reported in previous literature [12 ,13 ,21 ].Furthermore, the voltage on/off ratio was calculated to be ≥3 × 10 4 even by considering the noise as the off-state signal.Furthermore, the dual-gated mapping of V xx (Fig. 2 b) exhibits that V xx always approaches zero in the region of V bg ≥ 0 V.When V bg is < 0 V, the V xx rises with the wellknown Dirac features, suggesting the dominant role of graphene in total transport.Meanwhile, the carrier mobility extracted was ∼20 0 0 0 cm 2 V −1 s −1 at T = 120 K (see Supplementary Section S2.5 ).Moreover, the voltage at the Dirac point scales up with decreasing V bg because the V bg -activated conducting BP channel screens the V bg and contributes to the total output voltage (detailed discussion in later section).
It is known that the transverse signal of ideal graphene is negligible in the absence of a magnetic field due to the weak spin-orbital coupling in graphene [43 ].In contrast, the transverse voltage ( V xy , Electrodes 7 and 3, inset in Fig. 2 c) here is non-zero and reaches the maximum at V bg = 0 V.In addition, the transverse voltage vs V tg curves (Fig. 2 d  gests that the displacement field from the back-gate voltage partially penetrates the BP to modulate the carrier density of the graphene.While V bg < 0 V, the d V tg /d V bg turns into zero resulting from complete screening of V bg by the BP layers.
To theoretically quantify the longitudinal and transverse responses, we developed a paralleltransport model by incorporating an in-plane junction and gate-switchable electrical connection.We first defined a parallel propagation coefficient that characterizes the transverse signal reduction by the increment of BP conductivities: where subscripts 51 and 73 represent the injecting current from Electrodes 5 to 1 and capturing the voltage difference between Electrodes 7 and 3. η equals 1 for insulating BP ( V bg ≥ 0 V) and drops with increasing BP conductivity from hole accumulations ( V bg < 0 V).Considering the electrostatic screening effect, we derived the following function: which links the unstrained and strained (annealed) graphene through the conducting BP layer.Modified by the parallel propagation coefficient, therefore, the V xx at the on-state actually reflects the volt-age variation in pristine graphene ( V 51,710 ).The independence between η and V tg determines the onstate function V xx ( V tg ) following the same manner as V 51,710 ( V tg ).Additionally, the electronic structure of unannealed graphene remains uninterrupted and dominates the high carrier mobility of graphene devices.On this basis, the simulated evolutions of both V xx and V xy (Fig. 2 e and f) with dual gates perfectly match with our experimental data (Fig. 2 b and d).
The gate-switchable conduct-insulate states of the BP and the electrical connection contribute to the concurrence of a high on/off ratio and mobility in the graphene monolayer.

PROPOSED WORKING PRINCIPLES
In accordance with the electrostatic screening effect, our device exhibits a surface propagation mode whereby the charges are electrically polarized at the top graphene/BP interface and bottom BP/hBN interface [33 ].Graphene possesses better conductivity at the top interface and dominates the charge transport especially at low operation bias.For simplicity, we employed graphene to represent the top interface (see Supplementary Section S2.3 ).At the bottom interface, accumulating surface charges at the BP/hBN interface enable bottom BP layer conductivity [44 ,45 ].When V bg ≥ 0 V, the Fermi energy lies within the BP bandgap and the bottom BP channel is depleted (Fig. 3 a).After injecting current flow from Electrode 5 to Electrode 1, electrons are restricted within the unannealed region (orange path, Fig. 3 b) by the reflective interface, producing a zero voltage potential between the Electrodes 3 and 2 and grounded Electrode 1.Meanwhile, the transverse V xy referring to the electrostatic potential at Electrode 7 is governed by the graphene resistance ( R 71 ) and becomes non-zero (Fig. 2 c and d).This hypothesis was reconfirmed using inter-electrode Landauer-Büttiker transmissions that prohibit charge transmission across the reflective interface within an in-plane strain junction (see Supplementary Section S2.6 ).
One superiority of the Gr/BP interface lies in the formation of an in-plane reflective interface via partially annealing to guide the charge flow and regulate the voltage.When V bg < 0 V, the bottom BP channel becomes conductive and propagates in parallel with the graphene.The thickness of the conducting BP bottom channel is estimated to be ∼3 nm due to the well-known screening effect [46 ].More importantly, the edge-contact electrodes connect Electrode 3 (annealed region) and Electrode 7 (unannealed region) via the bottom BP channel.Note that the charge tunneling probability between the  S1 ).
graphene and the bottom BP channel exponentially decays with increasing BP thickness and becomes ignorable for a thick tunneling barrier ( > 10 nm) in our devices.Consequently, a Hall-like transverse current ( J y ) flow in the bottom BP channel (red solid lines in Fig. 3 c) balances the electrostatic potential difference over the reflective interface.Non-zero I 32 as well as V 32 is then developed, as demonstrated by the equivalent circuit i l lustrated in Fig. 3 d.Guided by this, we are able to switch the bottom BP channel from the off-state into highly mobile on-state by using the back-gate toward high on/off ratios in graphene.

ROBUSTNESS AGAINST MAGNETIC FIELD AND TEMPERATURE
To simulate real-world working conditions, the graphene-based transistor was exposed to magnetic fields ( B = ±12 T) and the V xx -V bg curves (Fig. 4 a) at T = 120 K reveal two notable features.First, the transistor remains in the off-state at V bg ≥ 0 V even when being exposed to perpendicular magnetic fields.This indicates that the in-plane strain junction is robust and deflects all the charges even under cyclotron motions and Hall fields.Second, the magnitude of the on-state responses at ±12 T evolves differently for V bg < 0 V and becomes negative at + 12 T in the range of −8 V < V bg < 0 V.To gain a better understanding of the asymmetric magneto-conductance, we mapped the magneto-asymmetric component V as -xx as functions of the magnetic field and V bg (Fig. 4 b), where V as -xx was extracted according to For the on-state, V as -xx exhibits a sign reversal when switching magnetic fields from negative to positive, which is identical to the Hall effect of a bridge current.Therefore, the overall output voltage is the superposition of the voltage component from J x and the Hall-like signal from J y , revalidating our assumption of the parallel propagation model (Fig. 3 c).Figure 4 c shows the 2D mapping of V xx as functions of dual gates at B = 12 T and the ideal off-state (at V bg ≥ 0 V) demonstrates the robustness of our transistor against magnetic disturbances.
In addition to the magnetic-field considerations presented above, the off-state of the graphene-based transistor (Fig. 4 d) remained near zero at room temperature, resulting in an impressive on/off ratio of up to ∼2 × 10 3 , even when the noise voltage of ∼0.02 μV (limited by lock-in instruments, I bias = 100 nA) was taken into account when esti-mating the off-state signal.Additionally, the roomtemperature electron mobility of the graphenebased transistor was determined to be ∼80 0 0 cm 2 V −1 s −1 .Here, the bridge current relies heavily on the Schottky barrier between the BP and metal contacts.The bandgap of the BP was found to increase monotonically with elevated temperature [47 ], which enlarged the Schottky barrier that constrains thermally excited carriers, thus facilitating robust voltage switching at room temperature.
Figure 4 e presents a comparison of the on/off ratio and mobility of our graphene-based transistor with those of typical semiconducting material devices reported in previous literature.Although transition metal dichalcogenides typically exhibit on/off ratios of > 10 5 , their mobility (200-410 cm 2 V −1 s −1 ) is severely limited due to the strong phonon scattering [48 ] as compared with the predicted mobility values for silicon, which are higher for holes ( ∼650 cm 2 V −1 s −1 ) and electrons ( ∼1400 cm 2 V −1 s −1 ) [49 ].Toward high on/off ratios, our graphene-based transistor employs a semiconducting BP channel and an in-plane strain junction, while a non-annealed graphene channel delivers exceptional mobility, surpassing the L-region of prior performance data.Simultaneously achieving a high on/off ratio and carrier mobility offers the potential for reducing power consumption in highperformance integrated circuits.

CONCLUSIONS
In conclusion, we have developed a graphene-based transistor that boasts an excellent on/off ratio ( > 10 3 ) and high carrier mobility ( ∼80 0 0 cm 2 V −1 s −1 ) at room temperature.It is generally believed that achieving a complete off-state and high on/off ratio is not feasible for high-mobility graphene.We show that local annealing of monolayer graphene, interfaced with substrates that are mismatched in terms of symmetry and crystal lattice, can result in a nearzero off-state.Notably, the resulting high on/off ratio is robust against magnetic fields and elevated temperatures, and is voltage-based, which can be conveniently converted into a current-based ratio, in accordance with Ohm's law for diverse application scenarios.Moreover, the off-states are constrained by the noise signal level determined by the lock-in measurement, indicating that an upsurge in current bias can lead to a higher on-state signal and a greater on/off ratio.While our research has only examined the combination of graphene and BP, it is expected that overlaying graphene on black arsenic, SnSe and their homologs wi l l yield simi lar coexistence of a high on/off ratio and carrier mobility in a single graphene transistor at room temperature.This development wi l l enable graphene transistors to be integrated into modern circuits with reduced power consumption.

Fabrication of the graphene-based devices
The cleavage of layered material sheets onto SiO 2 /Si substrates was achieved utilizing blue 'magic' tape.An exfoliated BP or graphene flake with a straight edge and well-defined geometry was selectively utilized.Raman mapping was then adopted to distinguish the zigzag or armchair nature of the crystal edges.To avoid any degradation, both the exfoliation and the transfer processes involving the BP were executed within a glove box under an argon atmosphere, with the oxygen and water levels maintained at < 0.1 ppm.
Following this, we adhered the hBN-graphene-BP heterostructure using a well-established drytransfer technique [50 ].We first prepared a hybrid film comprising 5 wt% of poly(bisphenol A carbonate) (PC) and 15 wt% of polypropylene carbonate (PPC).The PC layer served as an adhesive to pick up the 2D materials selectively while the PPC layer was liquefied to preclude the formation of interlayer bubbles.This hybrid film was then placed atop a polydimethylsiloxane (PDMS) stack for additional manipulation.Ultimately, we treated the PDMS surface with O 2 plasma (Femto Plasma Etcher) under 50 sccm and 50 W for 1 min to enhance the surface adhesion with the PC/PPC film and prevent delamination during the transfer process.
The specific dry-transfer procedure is as follows: the top hBN layer was lifted at 70°C.Consecutively, the graphene and BP flakes were assembled together at 120°C.During the graphene/BP assembly, the zigzag edges of the two materials were aligned (0°) or misaligned (15°) using a well-established transfer platform with a rotatable plate.After that, the assembled heterostructure was finally released onto the SiO 2 /Si substrate at 180°C.Subsequently, standard electron beam lithography was carried out to define the device geometry using a polymethyl methacrylate mask, followed by CHF 3 /O 2 ion etching.Cr/Au (3/70 nm) was thermally deposited to form edge contacts.Layer thickness was verified using a Bruker Dimension FastScan AFM in tapping mode.

Electrical measurements
We performed measurement (excitation frequency ∼13.373Hz) and standard Hall measurement using the TeslatronPT system (Oxford Instrument).The DC current of 100 nA was applied to avoid Joule heating.Local current annealing was performed with 1 mA/ μm of DC current at 300 K for 120 min.

Figure 1 .
Figure 1.Dual-gated graphene transistor.(a) Atomic structure of Gr (top panel) and BP (bottom panel).(b) Schematic of graphene transistor.The flat and rippled regions represent unannealed and annealed Gr, respectively.The right panel sketches the side view of the transistor.(c) Raman spectra of unannealed (blue curve) and annealed (red curve) sample regions.For clarification, the peaks at 1365.7 cm −1 originate from the in-plane mode of the hBN crystal [51 ].(d) The FWHMs of G and 2D peaks collected from the unannealed (blue dots) and annealed (red dots) regions.(e) Differential conductance vs applied DC-bias plots for unannealed (Electrodes 6 and 7) and annealed (Electrodes 2 and 3) sample regions at 1.5 K. Curves were vertically shifted for clarity.Schematic of (f) atomic structure of pristine Gr/BP stack and (g) simulated Gr band structure.(h) Proposed structure of annealed Gr/BP region and (i) corresponding band structure of Gr.

Figure 2 .
Figure 2. Unconventional voltage transition in graphene transistor at 120 K and I bias = 100 nA.(a) Longitudinal voltage ( V xx , Electrodes 3 and 2) as a function of V bg .The inset shows the corresponding configuration.(b) Experimental dual-gated map of V xx .(c) Transverse voltage ( V xy , Electrodes 7 and 3) as a function of V bg .The inset sketches the configuration for V xy .(d) Experimental dual-gated map of V xy .Simulated dual-gated maps of (e) V xx and (f) V xy , respectively.
) show a typical Dirac feature at different V bg , indicating an inhomogeneous current flow within the graphene.The finite slope (d V tg /d V bg ) of the Dirac point at V bg ≥ 0 V sug-

Figure 3 .
Figure 3. Operation mechanism of graphene-based transistor.(a) Inhomogeneous current flow within Gr channel.When BP is insulating, the voltage of annealed Gr is zero, representing Boolean '0' state.(b) Effective resistor network for Boolean '0' state.Current path is highlighted in orange.(c) Dual-channel propagations of graphene and BP bottom layer.Non-zero V o represents Boolean '1' state.Electrodes bridge graphene and BP bottom channels at each pin point denoted as red dashed lines.Red solid lines represent bridge currents at BP bottom channel.(d) Equivalent resistor network for Boolean '1' state.R 73, B and R 102, B denote the resistance of the BP bottom channel.The activated current channel is highlighted in blue.

Figure 4 .
Figure 4. Device performance at different magnetic fields and temperature.(a) V xx as a function of V bg for B = −12 T (red), 0 T (green) and 12 T (blue) at T = 120 K and V tg = −6.2V.The negative V xx that emerged at −8 V < V bg < 0 V is due to a dedicated interplay between the magnetic-field-induced Hall signal and the strain-junction-induced Hall-like one in the BP bottom channel.(b) Extracted V as -xx as functions of B and V bg .(c) Dual-gated map of V xx at T = 120 K and B = 12 T. Negative V xx is highlighted in orange.(d) Magnetic-field-dependent V xx -V bg evolution at T = 300 K and V tg = 0 V.The curves in red, green and blue correspond to the data collected at B = −12, 0 and 12 T, respectively.For comparison, the data collected at T = 120 K and V tg = 0 V (dashed orange curve) is also presented.(e) Room-temperature on/off ratio and carrier mobility of FETs based on various semiconductors including metal oxides, transition metal dichalcogenides and puckered semiconductors ( Supplementary TableS1).